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Overview Maxim's high-speed serializer and deserializer (SerDes) products have been used in video, image, and data transmission in automobiles, networks, servers, and 3G base stations. The MAX9247 serializer and MAX9218 deserializer form a pair of typical single-channel LVDS links with embedded clocks. The highest serial data rate of this link can reach 800Mbps.
This application note discusses the performance of the data transceiver link under different cable types, cable lengths, and data rates, as well as the performance improvements brought by Maxim ’s proprietary pre-emphasis technology and line equalization technology. In order to meet the requirements of harsh environments in automotive applications, the serializer / deserializer (SerDes) chipset was tested in the temperature range of -40 ° to + 105 ° C. Test equipment The test equipment includes an Agilent ParBERT 81250 tester, TDS784C 1GHz digital oscilloscope, TEK P6247 differential probe and MAX9217 / MAX9218 evaluation board. Agilent 81250 is a parallel bit error rate tester (BERT). The connection of these devices is shown below (Figure 1). 
Figure 1. MAX9247 and MAX9218 performance test setup
The MAX9247 has 27 parallel data inputs, of which 18 are RGB video data inputs and 9 are control inputs. The data rate of the LVDS serial link is 20 times the parallel data rate and includes 2 additional bits. The first 9 output channels of the Agilent 81250 are connected to the first 9 RGB inputs (RGB_IN0 to RGB_IN8). The reverse output of the first 9 channels is connected to the remaining 9 RGB inputs (RGB_IN9 to RGB_IN17), and the bit error rate tester (BERT) only detects RGB data. The data sequence of each output channel of ParBERT is independently generated, and there is no repeated pseudo-random sequence bit stream within the length of 21492. The length of the RGB data sequence is 1370 bits. Add a 20-bit time interval after 1370 bits as the control period. All control bits (CNTL_IN0 to CNTL_IN8) are usually set to 0. Figure 2 shows the data structure. This 1390-bit parallel data format appears repeatedly in the test, and the signal DE_IN alternately changes the RGB data period and control period. 
Figure 2. Sequence structure of test data Test conditions and measurement results We tested three pairs of twisted pair cables, as shown in the following table.
Table 1. Types of cables tested Manufacturer Part Number Length (M) Comments NISSEI SIODIC F-2WME, AWG26 10, 20, 30 Shielded SIODIC F-2WME, AWG28 10, 20, 30 General Cable CAT5E, AWG24 10, 20, 30 Unshielded JAE MX38 20 Shielded
In order to test the performance of the serializer / deserializer (SerDes) chipset and the relationship between cable length and data rate, we observed the bit error rate (BER) of different cable lengths and recorded the time when there was no error within 10 minutes. Maximum parallel data rate. The data rate increment is 1Mbps. We use this method to measure performance based on two considerations of the LVDS SerDes transceiver: first, if there is no error within 10 minutes, it is likely that there will be no error within a few hours; second, Even if the bit error can be observed within ten minutes even at a very low rate, then a small data rate increment (<0.5Mbps) will also cause the DE_OUT signal on the deserializer to lose lock. Therefore, our method is a reasonable compromise between test time and test reliability. Therefore, we can assume that at a certain data rate, if no bit errors occur within ten minutes, the bit error rate (BER) of the link is less than 10-10 or 10-11. According to statistics, we can use Equation 1 to calculate the confidence of this hypothesis: 
Where N is the number of bits transmitted through the serial link during the observation period (for example, 10 minutes), and p is the assumed bit error rate (BER). Table 2 shows the confidence for different data rates.
Table 2. Relationship between confidence and data rate observed in 10 minutes
Test results shown in Table 3 are the performance obtained under different cable types, cable lengths and data rates, as well as pre-emphasis and LVDS equalizer enable or disable. The pre-emphasis function is integrated in the MAX9247, which can be enabled by setting the jumper JP15 on the evaluation board to a high level. The proprietary LVDS equalizer is placed at the LVDS output of the MAX9247, as shown in Figure 1. For details of the implementation of the equalizer, please contact Maxim's application technical support. All data in Table 3 were obtained at room temperature. The test results of the 30m NISSEI AWG26 cable in the extended temperature range are shown in Table 4. Parallel Data Rate (Mbps) Number, N, of Bits
Transmitted by the
Serial Link in Ten Minutes Confidence Level of p BER <10-10 BER <10-11 10 12 x 1010 > 99.999% 69.88% 20 24 x 1010 > 99.999% 90.92% 30 36 x 1010 > 99.999% 97.27% 40 48 x 1010 > 99.999% 99.18%
Table 3. Reliable data rates of SerDes transceivers tested under different conditions Cable Type Pre-Emphasis LVDS Link Equalizer Maximum Reliable Serial Data Rate (SDR) Cable Length 10m 20m 30m PCLK (MHz) SDR (Mbps) PCLK (MHz) SDR (Mbps) PCLK (MHz) SDR (Mbps) NISSEI AWG26 Off Off 34 612 25 450 15 270 On Off 40 720 27 486 17 306 Off On 38 684 34 612 30 540 On On 43 774 39 702 35 630 NISSEI AWG28 Off Off 33 594 16 288 8 144 On Off 36 648 twenty three 414 10 180 Off On 35 630 33 594 twenty three 414 On On 41 738 37 666 28 504 General Cable CAT5e Off Off 38 684 26 468 16 288 On Off 42 756 28 504 18 324 Off On 38 684 35 630 32 576 On On 44 792 42 756 36 648 JAE MX38 Off Off 16 288 On Off twenty four 432 Off On 35 630 On On 40 720
Table 4. Reliable data rates of SerDes transceivers measured in the extended temperature range (*) Cable Type Maximum Reliable Serial Data Rate (SDR) Temperature -40 ° C 25 ° C 105 ° C PCLK (MHz) SDR (Mbps) PCLK (MHz) SDR (Mbps) PCLK (MHz) SDR (Mbps) NISSEI AGW26, 30m 36 648 35 630 31 558
* Note: In this test, the pre-emphasis function and the LVDS equalizer are both enabled.
The eye diagram below is recorded at the LVDS input port of the deserializer. These graphic displays understand the serializer's ability to recover data from distorted symbols. We can also see in the eye diagram that the LVDS link equalizer significantly improves the signal. 
Figure 3. NISSEI AWG26 cable, 20m long, rate 702Mbps, with pre-emphasis and equalizer enabled 
Figure 4. NISSEI AWG26 cable, 30m long and 630Mbps, with pre-emphasis and equalizer enabled 
Figure 5. NISSEI AWG26 cable, 30m long, at a rate of 306Mbps, with pre-emphasis enabled 
Figure 6. NISSEI AWG26 cable, 30m long, at a rate of 306Mbps, with pre-emphasis enabled and equalizer. Summarizing the results shown in Table 3 and Table 4, we can draw the following conclusions: Although the performance of CAT5E unshielded cable is better than the other two The type of cable is good, but it will have electromagnetic interference (EMI) problems in application. Pre-emphasis and LVDS equalization help improve link performance. Pre-emphasis can provide a greater improvement for short-distance cables, and the equalizer is more effective for improving long-distance cables. For a 30m cable, the equalizer can double its data transmission rate. The performance difference in the extended temperature range is relatively small. The wire gauge of the cable will restrict performance. It is recommended to use cables better than AWG28. References Maxim's high-speed interconnect design guide MAX9247 data sheet MAX9218 data sheet
MAX9247 / MAX9218 serializer / deserializer chipset performance test
Abstract: High-speed serialized data connections have been widely used for video display, digital camera, and backplane data transmission in networks, servers, and 3G base stations. Maxim has developed various products for serial transceiver links. This application note discusses the performance of typical serializer and deserializer (SerDes) chipsets (MAX9247 and MAX9218) at different cable types, cable lengths, and data rates . The conclusion can be used as an application guide for high-speed serial data interconnection.